Download any of these IConnect® application notes on this page for free. Each of application note describes using the Tektronix™ TDR Systems and IConnect® to solve specific interconnect measurement applications to include: Improving impedance measurement accuracy, create differential S-parameters from TDR/T measurements for extracting interconnect bandwidth, create accurate SPICE models from TDR measurements and more.
Use GigaProbes with IConnect and your Tektronix TDR system for complete Transmitter to Receiver analysis
Tektronix comprehensive, integrated tool set for the latest high-speed serial technologies. Connect a GigaProbes® on each end of the serial transmission interconnect for TDR/TDT verification, S-Parameter measurement, Jitter, Noise and BER analysis -enables you to resolve design challenges quickly and efficiently. Tektronix Equalization and Channel Emulation capabilities ensure you can see the effect of the channel on the eye and observe a realistic signal at the input of your receiver. As serial data speeds increase, loss and distortion caused by the channel must be equalized in the receiver for the signal to be recognizable. Meanwhile, effects of loss and crosstalk must be fully verified in both time- and frequency-domains. A powerful, flexible test solution that addresses these requirements maximizes characterization throughput and improves time to market.
This technical note presents single-ended insertion loss ( SE IL) and return loss ( SE RL) data generated from two different methods: 1) vector network analyzer (VNA), and 2) TDA Systems IConnect®. The purpose of this note is to validate the use of the IConnect® software in generating these parameters as an alternative to the more widely accepted VNA generated data.
TDR and S-parameters Measurements – How Much Performance Do You Need? Summary In this paper we identified, based on expert user knowledge, accuracy requirements for SDNA debug, compliance, validation, and characterization applications. We defined the following requirements for SDNA applications: ·TDR rise time to resolve smallest relevant discontinuity ·TDR rise time for standard characterization ·Dynamic range and bandwidth requirements for ·Standards characterization Summary of Topics Discussed Serial Data Network Analysis (SDNA) Application, TDR Spatial Resolution Requirements, TDR Spatial Resolution Requirements, Frequency Domain Dynamic Range and Bandwidth Requirements for Serial Standards, Dynamic Range Requirements for Serial Data, Frequency Requirements for Serial Data, Tektronix TDR Modules
TDR Impedance Measurements: A Foundation for Signal Integrity Summary: Signal integrity is a growing priority as digital system designers pursue ever-higher clock and data rates in computer, communications, video and network systems. At today’s high operating frequencies, anything that affects a signals rise time, pulse width, timing, jitter or noise content can impact reliability at the system level. To ensure signal integrity, it is necessary to understand and control impedance in the transmission environment through which the signals travel. Mismatches and variations can cause reflections that decrease signal quality as a whole. Impedance tolerances are part of the electrical specifications for many of today’s digital system components, including Firewire, PCIe, SATA, DisplayPort and more. It is standard practice to use modeling tools to design high-speed circuits. Modeling hastens the design cycle and minimizes errors. However, modeled designs must be verified with hardware measurements, including impedance measurements, after the prototype is built. The methodology of choice for measuring impedances is Time Domain Reflectometry (TDR), carried out using high-performance instruments such as the DSA8200 oscilloscope equipped with the 80E04 TDR sampling module. TDR permits the signal transmission environment to be analyzed in the time domain just as the signal integrity of data signals is analyzed in time domain Legacy IConnect Application Notes Complete Methodology for Signal Integrity Analysis of Gigabit Interconnects
IBM BladeCenter Simulation Using IConnect This paper will describe how IConnect™ software was used during BladeCenter development to do signal integrity simulation. Using Measure-Based Modeling to AnalyzeBackplane Deterministic Jitter This paper specifically deals with using measure-based modeling of deterministic jitter contributors in a concise and verifiable methodology. Serial ATA Development by Michael Cheong, Molex, and Dima Smolyansky, TDA. Both Serial ATA specification testing and Molex cable assembly modeling are discussed. Lossy Line Simulation and Analysis The effect of frequency dependent losses on the interconnect link performance is primarily in degradation of rise time, amplitude, and eye diagram. The rise time for the signal transmitted through a link slows down as a result of losses, and the signal amplitude decreases. The amplitude, however, does not stay at a permanently lowered level, as it would in a case of purely DC loss. In fact, it gradually creeps up towards the incident signal amplitude. However, the losses can delay the signal to the point that it effectively looks as if it never reaches that incident signal level. Introduction to TDR Eye Diagrams Eye diagram is becoming a key figure of merit for most computer and communications system standards, including Gigabit Ethernet, Sonet, Infiniband, Rapid IO, PCI Xpress and others. Even though some designers would rightfully argue that insertion and return loss are more important and representative of the performance of the interconnect at a given speed, eye diagram provides a clear visual representation of whether the interconnect by itself would meet the eye diagram test specification for a given standard. GigaBit Model Study on High Speed cables using IConnect Purpose of study: To determine the viability of using TDR based measurements and software to extract SPICE models for use in running performance simulations of Gbit links.– Identify strengths and weaknesses of the approach – Determine what can be safely modeled and what must be measured • Method:– Measurements of cable assemblies, test fixtures(TDR/TDT) – Extraction of SPICE models from measurements – Eye pattern measurements – Performance simulation using SPICE models – Comparison of results. This is a • This is work in process exercise • Joint effort of:– Mark Marlett Cypress Semiconductor– Dima Smolyansky TDA Systems – John Sawdy Meritec – Chris Shmatovich Meritec TDR Test Primer Time Domain Reflectometry (TDR) has traditionally been used for locating faults in cables. Currently, high-performance TDR instruments, coupled with add-on analysis tools, are commonly used as the tool of choice for failure analysis and signal integrity characterization of board, package, socket, connector and cable interconnects at gigabit speeds. Based on the TDR impedance measurements, the designer can perform signal integrity analysis of the system interconnect, and the digital system performance can be predicted accurately. TDR and VNA Test Primer Two basic measurement techniques exist for signal integrity characterization of gigabit interconnects in digital systems - Time Domain Reflectometry (TDR) and frequency domain Vector Network Analysis (VNA). This paper discusses the benefits and tradeoffs of both measurements techniques. (tvmp-0404.pdf) Interconnect Probing Quick Guide Probe Quick Tips, Mechanical and Electrical Interfaces for the Probes and the DUT, Defining the Required Probe Bandwidth, Probing and Fixturing Approaches Pros and Cons.(iconnect_probing.pdf) Signal Integrity Modeling of Gigabit Backplanes, Cables and Connectors Using TDR TDR-Based Modeling Methodology, RLC Connector and Package Modeling, Impedance Profile Modeling of Backplanes and Cable Assemblies, Differential Transmission Line Modeling Techniques, Lossy Line Modeling Techniques, Putting It All Together:Example 1: Cable-Connector-PCB fixture characterization, Example 2: Lossy Symmetric Differential Backplane Characterization, Example 3: Lossy Symmetric Backplane, Including the Even Mode. (GIGA-0502) Measurement of Mutual Inductance and Capacitance in the Presence of Arbitrary Termination In this technical brief, we derive the equations for mutual inductance and capacitance measurements under arbitrary termination conditions, and define how C mutual and L mutual computations in IConnect® TDR software are affected by the impedance values of these terminations. Measurement M-LVDS Input and Output Die Capacitance vs. Input Voltage Using TDR Input capacitance of the buffer will affect the overall signal integrity of the digital circuit, and knowing this capacitance is important to understand the circuit performance. (Measurement M-LVDS Input and Output Die Capacitance vs. Input Voltage Using TDR.doc) TDR IConnect® Modeling Quick Guide
Practical Characterization of Lossy Transmission Lines Using TDR Losses in digital interconnects were not very important at the lower frequencies, but as the communications and computer system designs are moving into the gigahertz territory, this picture changes rapidly. High-frequency effects such as skin effect and dielectric loss begin to affect signal integrity in these high-speed digital systems in the most profound manner, and therefore must be understood and characterized. (loss0601.pdf) Characterization of Differential Interconnects from TDR Measurements Differential signaling schemes are a common approach to achieving higher noise immunity for critical signals in a high-speed digital design.Measurement and modeling of the transmission lines carrying differential signals, however, pose several different challenges that need to be addressed in order to achieve an accurate picture of differential signal transmission in digital system design and simulation. (diff1199.pdf) TDR Characterization of ATE Fixturing Boards and Sockets Signal integrity in ATE fixture boards, also referred to as load boards or Device Under Test (DUT) interface boards, is a key part of achieving a high quality, low noise test environment. At-speed testing places severe requirements on the quality of load boards, demanding minimal signal distortion at speeds of several hundred megahertz and subnanosecond rise times. Distortion of the test signals delivered to the DUT and the signals received by the tester comparators results in test errors, rejection of working arts, and, even worse, acceptance of faulty ones, costing the manufacturer thousands, or even millions or dollars. In this article, we will discuss characterization of ATE fixturing using TDR measurement methodology, and offer some suggestions on how this characterization data can be used to avoid unnecessary test failures. As a result of careful ATE load board analysis, more accurate production test limits can be set. Test engineers can use detailed load board characterization data to model the device performance accurately in the test environment, and to ensure accurate interpretation of test results. With accurate characterization data, test engineers can improve overall test yield for their ICs, resulting in significant savings for the IC manufacturer. (fixt1000.pdf) Disk Drive Flexible Interconnect Characterization Using TDR Increased demands on the disk drive industry for higher performance, data throughput, and speed have resulted in a transition from the use of twisted pair interconnect to flexible board interconnect, to connect disk drive read/write heads and the preamplifier. The flexible board interconnect provides better mechanical properties and electrical impedance control, while creating new possibilities for placing the pre-amplifier closer to the disk drive head, which overall provides a logical path for achieving a higher data throughput for the industry. With increasing data rates and signal rise times, the need for signal integrity SPICE and IBIS-type simulations of the signal propagation through the flexible interconnect in the disk drives has increased. The needs for disk drive interconnect characterization and equivalent circuit model accuracy have increased accordingly. (flex0500.pdf) PCB Interconnect Characterization From TDR Measurements As the performance requirements for modern computer and communications systems grows, the demand for high speed Printed Circuit Boards (PCB) increases as well. Speeds as fast as 1Gbit/sec are expected to be supported by standard PCB technologies, with the rise times of these signals being as fast as 100ps. At these speeds, interconnections on PCBs behave as distributed elements, or transmission lines, and reflections due to impedance mismatch are a typical signal integrity problem that board designers encounter in their work. Vias between layers and connectors on a board create discontinuities that distort the signals even further. To accurately predict the propagation of the signals on a board, designers need to determine the impedance of their traces on different layers and extract the models for board discontinuities. Time Domain Reflectometry (TDR) measurements have always been the measurement approach of choice for board characterization work. Based on TDR measurements, a circuit board designer can determine characteristic impedances of board traces, compute accurate models for board components, and predict board performance more accurately. Single Trace and Power Plane Shorts Fault Isolation Using TDR Techniques for locating open faults with Time Domain Reflectometry (TDR) oscilloscopes have been successfully demonstrated in papers presented at ISTFA 1999  and 2000 . It has been shown that obtaining the true impedance profile using TDA Systems' IConnect® TDR software , or other implementations of the impedance deconvolution algorithm,allows locating the faults in the packages more repeatably and predictably, and in  a number of techniques using the impedance profile have been presented. For example, one of the key impedance profile features differentiating an open fault in the package or bondwire from an open fault in the die itself is a dip in the impedance profile corresponding to an input die capacitance and presenting itself shortly before the open impedance signature. The presence of this characteristic dip in the impedance profile indicates a good connection to the die, whereas its absence indicates a problem in the package structure. Such a capacitive signature can be observed much more readily on the impedance profile waveform than on a raw TDR waveform. In this report our focus is on locating short failures, using TDR-based fault isolation system. The failures include signal-to-ground shorts and plane-to-plane shorts. Examples of plane-to-plane shorts may be a power plane to a ground plane short, or a short from one power plane to another, inside the package or inside the die. Electronic Package Failure Analysis with TDR Time Domain Reflectometry (TDR) measurement methodology is increasing in importance as a nondestructive method for fault location in electronic packages . The visual nature of TDR makes it a very natural technology that can assist with fault location in BGA packages, which typically have complex interweaving layouts that make standard failure analysis techniques, such as acoustic imaging and X-ray , less effective and more difficult to utilize. In this paper, we will discuss the use of TDR for package failure analysis work. We will analyze in detail the TDR impedance deconvolution algorithm as applicable to electronic packaging fault location work, focusing on the opportunities that impedance deconvolution and the resulting true impedance profile opens up for such work. TDR Techniques for Characterization and Modeling of Electronic Packaging Typical package characterization setup, Multiple Reflections and the True Impedance Profile, Choosing Model Type and Model Validity Range, Single-ended TDR Techniques, Impedance Profile Analysis Lumped Element Model Extraction, (JEDEC Guideline Method), Differential TDR Techniques :Even and Odd Impedance Analysis, Adjacent-Opposite Analysis.Selecting the Package Modeling, Method, Derivations: Lumped Model Circuit Description, Capacitance and Inductance of an Impedance Segment, Self and Mutual Capacitance and Inductance from Lumped Element Extraction Method, Lumped Self-Capacitance, Lumped Self-Inductance, Lumped Mutual Capacitance,Lumped Mutual Inductance, Self and Mutual Capacitance and Inductance from Even and Odd Impedance, Self and Mutual Inductance from Adjacent-Opposite. Remotely Launching Unix HSpice From Within IConnect TDA Systems provides two example scripts to be used for running HSpice simulations on a remote Unix machine as part of IConnect's integrated simulator interface.separate scripts are available for Windows NT/2000 and Windows 95/98.To use the Windows 95/98 script, it may be necessary to install third-party software.You will have to customize the scripts to some extent to get them to operate effectively on your network.(hnet1000.pdf) Ensuring Signal Integrity in Microprocessor Memory Boards and Memory Modules As the speeds of interface busses between the PC microprocessor and the memory go up, these busses begin to pose some unique design challenges for a digital designer. These challenges include increased signal reflections, crosstalk, and losses that must be analyzed and understood in order for a memory system to function properly. IBIS and SPICE simulations of microprocessor chipsets and memory systems are necessary to ensure that the signal propagates through the computer motherboard with minimal distortion, without causing erroneous switching patterns and signal degradation — ensuring the signal integrity in the motherboard design. The accuracy of such simulation depends completely on the accuracy of the models for the interconnect components of the digital design, such as board traces, connectors and packages. The accuracy of these models can be ensured with the use of TDR instrumentation, a very easy-to-use and intuitive technology for obtaining accurate models for the digital system components. (mmem1200-01.pdf) Direct RambusTM Signal Integrity Measurements Over the last ten years, computer processor architectures have done a remarkable job of increasing CPU performance. However, it is well known that main memory subsystems haven't kept pace with the blistering speeds of the microprocessor clocks. Although this gap has been bridged in part by improved and more sophisticated caches, data intensive images are demanding even more performance directly from the memory system. A significant development has recently changed the computer's systemarchitecture to solve this problem. Direct RambusTM is a high-speed digital bus that requires circuit board traces to be impedance controlled at 28 ohms. This two byte wide bus double pumps a 400 MHz clock to enable data transfer on both the rising and falling 2 HUG’99 clock edges. Assuming 100% utilization of the data bus, the peak bandwidth is amazing 1.6 GBytes per second.The traditional logic analysis measurement techniques now need to be complemented with a signal integrity measurement tool. Time Domain Reflectometry (TDR) is the tool of choice for digital design engineers today. (Rambus_Measurement_modeling_0699.pdf) SCSI Connector and Cable Modeling from TDR Measurements In this presentation, we will discuss interconnect modeling methodology based on TDR measurements, and illustrate it on a sample of SCSI flat ribbon cable with IDC connectors. Both single ended and differential measurements and modeling results will be presented.(scsi1299.pdf) Choosing Signal Integrity Measurement Tools: Time or Frequency Domain? To obtain accurate models for high-speed interconnects, a signal integrity engineer eventually needs to perform a measurement-based validation of the interconnect models. At that point, a choice needs to be made about the type of test equipment to be used to accomplish the job. Ease of use, accuracy, and cost are only a few of the attributes that will dictate the right instrumentation. The Time Domain Reflectometry (TDR) oscilloscope and the Vector Network Analyzer (VNA) are the two most common instruments used today. The choice between these two sometimes moves to a more theoretical choice between time and frequency domain measurements. Occasionally, it becomes a choice of personal belief in one domain being superior over the other. In reality, there are appropriate times for the use of both instruments. This paper will analyze the physics and mathematics of the relationship between time and frequency domain measurements. Practical aspects of testing will be discussed, as well as the ease of use and accuracy issues of the time and frequency domain measurement instruments. In conclusion, the paper will provide some practical suggestions on how to choose the right instrument for the application. (tdrd-0202.pdf)